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cy7c1069av33 2 m 8 static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05255 rev. *j revised november 29, 2010 2 m 8 static ram features high speed ? t aa = 10 ns low active power ? 990 mw (max) operating voltages of 3.3 0.3 v 2.0 v data retention automatic power down when deselected ttl-compatible inputs and outputs easy memory expansion with ce 1 and ce 2 features available in pb-free 54-pin thin small outline package (tsop) ii package functional description the cy7c1069av33 is a high performance complementary metal oxide semiconductor (cmos) static ram organized as 2,097,152 words by 8 bits. writing to the device is accomplished by enabling the chip (by taking ce 1 low and ce 2 high) and write enable (we ) inputs low. reading from the device is acco mplished by enabling the chip (ce 1 low and ce 2 high) as well as forcing the output enable (oe ) low while forcing the we high. see ?truth table? on page 8 for a complete description of read and write modes. the input/output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or during a write operation (ce 1 low, ce 2 high, and we low). the cy7c1069av33 is available in a 54-pin tsop ii package with center power and ground (revolutionary) pinout. logic block diagram a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps data in drivers power down we oe i/o 0 i/o 1 i/o 2 i/o 3 2048k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 14 a 13 a 17 a 19 a 15 a 16 a 9 a 18 ce 1 ce 2 a 10 a 11 a 12 a 20 [+] feedback
cy7c1069av33 document number: 38-05255 rev. *j page 2 of 12 contents selection guide ................................................................ 3 pin configuration ............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 dc electrical characteristics .......................................... 4 capacitance ...................................................................... 4 ac switching characteristics ......................................... 5 switching waveforms ...................................................... 7 truth table ........................................................................ 8 ordering information ........................................................ 9 ordering code definition ............................................. 9 package diagram .............................................................. 9 acronyms ........................................................................ 10 document conventions ................................................. 10 units of measure ....................................................... 10 document history page ................................................. 11 sales, solutions, and legal information ...................... 12 worldwide sales and design s upport ......... .............. 12 products .................................................................... 12 psoc solutions ......................................................... 12 [+] feedback
cy7c1069av33 document number: 38-05255 rev. *j page 3 of 12 selection guide description ?10 unit maximum access time 10 ns maximum operating current 275 ma maximum cmos standby current 50 ma pin configuration figure 1. 54-pin tsop ii [1, 2] top view we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 43 42 16 15 29 30 a 5 a 6 a 7 a 8 a 0 a 1 oe v ss a 17 i/o 7 a 2 ce 1 i/o 0 i/o 1 a 3 a 4 18 17 20 19 27 28 25 26 22 21 23 24 i/o 2 i/o 3 a 16 a 15 v cc i/o 6 nc i/o 5 i/o 4 a 14 a 13 a 12 a 11 a 9 a 10 ce 2 44 46 45 47 50 49 48 51 53 52 54 v ss v cc a 19 a 18 v cc v cc v ss dnu v ss nc v cc v ss nc nc nc nc nc nc nc nc a 20 notes 1. nc pins are not connected on the die. 2. dnu pins have to be left floating or tied to v ss to ensure proper application. [+] feedback
cy7c1069av33 document number: 38-05255 rev. *j page 4 of 12 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied ..... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc to relative gnd [3] .....?0.5 v to +4.6 v dc voltage applied to outputs in high z state [3] ................................... ?0.5 v to v cc + 0.5 v dc input voltage [3] ............................... ?0.5 v to v cc + 0.5 v current into outputs (low) ......................................... 20 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ? c 3.3 v ? 0.3 v industrial ?40 ? c to +85 ? c notes 3. v il (min.) = ?2.0 v for pulse durations of less than 20 ns. 4. tested initially and after any design or proces s changes that may affect these parameters. dc electrical characteristics over the operating range parameter description test conditions ?10 unit min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [3] ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ? a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max, f = f max = 1/t rc ? 275 ma i sb1 automatic ce power down current ?ttl inputs ce 2 < v il , max v cc , ce 1 > v ih v in > v ih or v in < v il , f = f max ?70ma i sb2 automatic ce power down current ?cmos inputs ce 2 < 0.3 v, max v cc , ce 1 > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 ?50ma capacitance tested initially and after any design or proces s changes that may affect these parameters. [4] parameter description test conditions tsop ii unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 6 pf c out i/o capacitance 8 pf [+] feedback
cy7c1069av33 document number: 38-05255 rev. *j page 5 of 12 figure 2. ac test loads and waveforms [5] notes 5. valid sram operation does not occur until the power supplies have reached the minimum operating v dd (3.0v). as soon as 1ms (t power ) after reaching the minimum operating v dd , normal sram operation can begin including reduction in v dd to the data retention (v ccdr , 2.0v) voltage. 6. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and transmission line loads. test conditions for the read cycl e use output loading shown in part a) of the ac test loads, unle ss specified otherwise. 7. this part has a voltage regulator which steps down the voltage from 3v to 2v internally. t power time has to be provided initially before a read/write operation is started. 8. t hzoe , t hzce , t hzwe and t lzoe , t lzce , and t lzwe are specified with a load capacitance of 5 pf as in (b) of ac test loads. transition is measured ? 200 mv from steady-state voltage. 9. these parameters are guaranteed by design and are not tested. 10. the internal write time of the memory is defined by the overlap of ce 1 low/ce 2 high , and we low. ce 1 and we must be low along with ce 2 high to initiate a write, and the transition of any of thes e signals can terminate the write. the input data setup and hold timing should be ref erenced to the leading edge of the signal that terminates the write. 90% 10% 3.3v gnd 90% 10% all input pulses 3.3 v output 5 pf* *including jig and scope (a) (b) r1 317 ? r2 351 ? rise time > 1 v/ns fall time: > 1 v/ns (c) output 50 ? z 0 = 50 ? v th = 1.5 v 30 pf* *capacitive load consists of all components of the test environment ac switching characteristics over the operating range [6] parameter description ?10 unit min max read cycle t power v cc (typical) to the first access [7] 1? ms t rc read cycle time 10 ? ns t aa address to data valid ? 10 ns t oha data hold from address change 3 ? ns t ace ce 1 low/ce 2 high to data valid ? 10 ns t doe oe low to data valid ? 5 ns t lzoe oe low to low z [8] 1? ns t hzoe oe high to high z [ 8 ] ?5 ns t lzce ce 1 low/ce 2 high to low z [8] 3? ns t hzce ce 1 high/ce 2 low to high z [ 8] ?5 ns t pu ce 1 low/ce 2 high to power up [9] 0? ns t pd ce 1 high/ce 2 low to power down [9] ?10 ns write cycle [9, 10] t wc write cycle time 10 ? ns t sce ce 1 low/ce 2 high to write end 7 ? ns t aw address setup to write end 7 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns [+] feedback
cy7c1069av33 document number: 38-05255 rev. *j page 6 of 12 t pwe we pulse width 7 ? ns t sd data setup to write end 5.5 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [8] 3? ns t hzwe we low to high z [ 8 ] ?5 ns ac switching characteristics over the operating range (continued) [6] parameter description ?10 unit min max figure 3. data retention waveform 3.0 v 3.0 v t cdr v dr > 2 v data retention mode t r ce v cc [+] feedback
cy7c1069av33 document number: 38-05255 rev. *j page 7 of 12 switching waveforms figure 4. read cycle no. 1 [11, 12] figure 5. read cycle no. 2 (oe controlled) [12, 13] notes 11. device is continuously selected. ce 1 = v il , ce 2 = v ih . 12. we is high for read cycle. 13. address valid prior to or coincident with ce 1 transition low and ce 2 transition high. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t asce t doe t lzoe t lzsce t pu high impedance t hzoe t pd high oe ce 1 impedance address data out v cc supply t hzsce current i cc i sb ce 2 [+] feedback
cy7c1069av33 document number: 38-05255 rev. *j page 8 of 12 figure 6. write cycle no. 1 (ce 1 controlled) [14, 15, 16] figure 7. write cycle no. 2 (we controlled, oe low) [14, 15, 16] switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw datai/o address ce we t t hd t sd t sce t ha t aw t pwe t wc data i/o address ce we t sa t lzwe t hzwe truth table ce 1 ce 2 oe we i/o 0 ?i/o 7 mode power h x x x high z power down standby (i sb ) x l x x high z power down standby (i sb ) l h l h data out read all bits active (i cc ) l h x l data in write all bits active (i cc ) l h h h high z selected, outputs disabled active (i cc ) notes 14. data i/o is high-impedance if oe = v ih . 15. if ce 1 goes high/ce 2 low simultaneously with we going high, the output remains in a high?impedance state. 16. ce above is defined as a combination of ce 1 and ce 2 . it is active low. [+] feedback
cy7c1069av33 document number: 38-05255 rev. *j page 9 of 12 ordering code definition package diagram figure 8. 54-pin tsop ii, 51-85160 ordering information speed (ns) ordering code package diagram package type operating range 10 CY7C1069AV33-10ZXC 51-85160 54-pin tsop ii (pb-free) commercial cy marketing code: 7= sram 7c 106 bus width: x8 density: 16 mbit technology: cmos company id : cy = cypress 9 a technology: 150 nm voltage: 3.3 v v33 51-85160 *a [+] feedback
cy7c1069av33 document number: 38-05255 rev. *j page 10 of 12 acronyms document conventions units of measure acronym description be byte enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package ttl transistor-transistor logic we write enable symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes mv milli volts mw milli watts ms milli seconds pf pico farad c degree celcius wwatts % percent [+] feedback
cy7c1069av33 document number: 38-05255 rev. *j page 11 of 12 document history page document title: cy7c1069av33 2 m 8 static ram document number: 38-05255 rev. ecn no. submission date orig. of change description of change ** 113724 03/27/02 nsl new data sheet *a 117060 07/31/02 dfp removed 15-ns bin *b 117990 08/30/02 dfp added 8-ns bin changing i cc for 8, 10, 12 bins t power changed from 1 ? s to 1 ms load cap comment changed (for tx line load) t sd changed to 5.5 ns for the 10-ns bin changed some 8-ns bin #'s (t hz , t doe , t dbe ) removed hz < lz comments *c 120385 11/13/02 dfp final data sheet added note 4 to ?ac test loads and waveforms? and note 7 to t pu and t pd updated input/output caps (for 48bga only) to 8 pf/10 pf and for the 54-pin tsop to 6/8 pf *d 124441 2/25/03 meg changed isb1 from 100 ma to 70 ma shaded the 48fbga product offering information *e 403984 see ecn nxr changed the logic block diagram on page # 1 added notes under pin configuration changed the package diagram of 51-85162 from rev *a to rev *d changed 48-ball fbga to 60-ball fbga in pin configuration updated the ordering information *f 492137 see ecn nxr removed 8 ns speed bin from product offering changed the description of i ix from input load current to input leakage current in dc electrical characteristics table updated the ordering information *g 2784946 10/12/2009 vkn/pyrs updated template corrected typo in footnote 9 updated ordering information table *h 2897049 03/25/10 aju removed inactive parts from the ordering information table. updated package diagrams. *i 2950666 06/11/2010 vkn removed 12ns speed bin, removed 60 ball fbga package updated ordering information added acronyms and ordering code definition . *j 3096933 11/29/2010 pras added units of measure . minor edits and updated in new template. [+] feedback
document number: 38-05255 rev. *j revised november 29, 2010 page 12 of 12 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1069av33 ? cypress semiconductor corporation, 2002-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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